1. Field of the Invention
The present invention relates to a semiconductor device. More particularly, the present invention relates to a power metal-oxide semiconductor (MOS) transistor technique.
2. Description of Related Art
A conventional MOS transistor layout is required to have an electrostatic protection ability for electrostatic discharge (ESD) when being applied to a power management circuit, in which a relatively large drain and source thereof are designed for bearing excessive currents and the ESD. However, this may lead to a poor integration of the MOS transistor layout. Moreover, excessively large metal wires connected between the drain and the source may also lead to an excessive voltage drop and excessive layout area.
FIG. 1 is a schematic diagram illustrating a layout of a conventional power MOS transistor. Referring to FIG. 1, the power MOS transistor 102 has a plurality of strip-shape gate structure layers 104 disposed on a substrate 100. A drain region 108 and a source region 106 are respectively allocated on the substrate 100 at both sides of the gate structure layer 104. By such means, the plurality of strip-shape transistors is connected in series to achieve the layout of the power MOS transistor, and functions as a current driving device. Such device includes a vertical redundant gate structure layer 104, and excessive length of a finger-shape metal wire used for connecting the drain region 108 and the source region 106 may lead to an excessive voltage drop and deviations of fabrication features of the devices thereof. Therefore, the metal MOS transistor may have poor features.
FIG. 2 is a schematic diagram illustrating a layout of a conventional power MOS transistor with ESD protection ability. Referring to FIG. 2, since the drain region 108 is required to bear a relatively large voltage generated by the ESD, a distance between a contact hole and a gate of the drain region 108 is enlarged, and meanwhile a metal wire connected to the drain region 108 is also enlarged. Relatively, size of the source region 106 is maintained unchanged, and therefore a width thereof is less than that of the drain region 108. By such means, affordability of the metal MOS transistor for the ESD is improved. However, such method requires a relatively large layout area.
Therefore, how to achieve a sufficient affordability for the ESD with a relatively small layout area is still an issue under development.